The present invention relates to semiconductor devices, and more particularly to a method and system for fabricating isolation structures in Flash memory devices.
Flash memory devices are semiconductor devices that are used to store data. Typically, a Flash memory device includes a core, which has memory cells, and a periphery, which includes other devices. The devices in the periphery include high voltage devices, such as charge generating circuits, and low voltage devices, such as amplifiers or control circuits. Separating the devices at the periphery, as well as the cells at the core, are isolation structures. Typically, these isolation structures are semiconductor trench isolation structures.
FIG. 1 depicts a conventional method 10 for providing conventional structures at the periphery of the Flash memory device. The conventional method provides conventional trenches where the isolation structures are desired, via step 12. The conventional trenches are then filled with a conventional oxide filler, via step 14. Typically, steps 12 and 14 are performed for both the core and the periphery. Thus, after step 14 is completed, isolation structures including an oxide filler will be present in both the core and the periphery. An oxide layer is then provided, via step 16. Typically, the oxide layer is approximately fifty Angstroms thick. Note that between steps 14 and 16, processing of the core is carried out. For example, an oxide-nitride-oxide layer may be formed. In addition, certain portions of the core, such as the tunneling barrier for memory cells in the core, are fabricated. Note that for some conventional Flash memory devices, the tunneling barrier is provided by a nitride oxide, such as N2O. However, during many of these processing steps, the periphery is typically not masked. Thus, the N2O will also be present at the periphery of the Flash memory device. Thus, the periphery of the Flash memory device is etched to reduce any remnant nitride, via step 18. The nitride might remain from fabrication of the tunneling barrier in the core, discussed above. The core of the conventional Flash memory device is then masked, via step 20. Thus, the periphery remains exposed after step 20. A gate oxide is then provided for a portion of the devices at the periphery of the conventional Flash memory device, via step 22. The gate oxide provided in step 22 is preferably a high voltage device gate oxide having a thickness of approximately 145 Angstroms. A portion of the periphery is then etched to remove the high voltage gate oxide, via step 24. This portion of the periphery includes low voltage devices, such as controllers or amplifier circuits. A low voltage gate oxide is then grown, via step 26. Fabrication of devices at the periphery then continues.
FIG. 2A depict a conventional Flash memory device 30 after fabrication of a portion of the devices at the periphery. The conventional Flash memory device 30 includes a core region 40, a high voltage region 50 and a low voltage region 60. The high voltage region 50 and low voltage region 60 are part of the periphery of the Flash memory device 30 because they are not included in the core 40. The core 40 includes a memory cell 42 having a tunneling barrier 46. The core 40 also includes a conventional isolation structure 44 separating the core 40 from the high voltage area 50. The high voltage area 50 includes a high voltage device 52 and a conventional isolation structure 54. The high voltage device 52 may include devices such as charge generating circuits. The high voltage region 50 also includes a gate oxide 56. The low voltage area 60 includes a low voltage device 62, a conventional isolation structure 64 and a gate oxide 66. Although only one device, one conventional isolation structure and one oxide layer are shown for each region 40, 50 and 60, each region 40, 50 and 60 typically has many isolation structures, devices and other structures.
Although the method 100 functions to provide the conventional Flash memory device 50, one of ordinary skill in the art will readily realize that the conventional Flash memory device 50 is subject to leakage due to degradation of the conventional isolation structures 54 and 64. FIG. 2B depicts a close up view of the conventional isolation structures 54 and 64, and device 62. The conventional isolation structures 54 and 64 include conventional trenches 51 and 61, respectively, that are filled with conventional oxide fillers 53 and 63, respectively. Near the corners 55, 57, 65 and 67 of the conventional isolation structures 54 and 64, the oxide filler 53 and 63 has thinned areas 58, 59 and 68. The thinned areas 58, 59 and 68 reduce the ability of the conventional isolation structures 54 and 64 to insulate devices 54 and 64. As a result, a leakage current can occur through the thinned areas 58, 59 and 68. The leakage current can lower the threshold voltage of devices fabricated near the conventional isolation structures 54 and 64, which adversely affect performance of the conventional Flash memory device 30.
The thinned areas 58, 59 and 68 may occur for a variety of reasons. Typically, silicon wafers having a (100) orientation (shown in FIG. 2B) are used for fabricating conventional Flash memory devices 30. Because the top surface has a (100) orientation, near the corners of the trenches 51 and 61, the exposed silicon has a (111) orientation. The (111) orientation of silicon has a larger number of dangling bonds. Thus, when the oxide filler 53 and 63 is provided in step 14 of the method 10 depicted in FIG. 1, areas near the (111) orientation are thinner. In addition, mechanical stress tends to concentrate at areas where a corner is fabricated. Mechanical stress also tends to cause a thinning of the oxide filler 53 and 63 near the corners 55, 57, 65 and 67 of the conventional isolation structures 54 and 64. In addition, as discussed above, in more recent conventional Flash memory devices, a nitride oxide, such as N2O is used in forming the gate oxide for the memory cells in the core region 40. When N2O is used, the thinning that results in the areas 58, 59 and 68 is even more severe. Thus, the problems due to leakage current in the devices 52 and 62 are made worse.
Accordingly, what is needed is a system and method for providing improved isolation structures. The present invention addresses such a need.
The present invention provides a method and system for providing a Flash memory device. The Flash memory device includes a core and a periphery. The method and system comprise providing the core for the Flash memory device and providing a plurality of isolation structures. A portion of the plurality of isolation structures is for isolating a plurality of devices at the periphery of the Flash memory device. Each of the plurality of isolation structures includes a corner and an oxide filler. The method and system further include providing the plurality of isolation structures by processing the plurality of isolation structures to reduce thinning of the oxide filler in proximity to the corner of the isolation structure.
According to the system and method disclosed herein, the present invention provides isolation structures which are less subject to thinning of the oxide filler near corners. As a result, isolation is improved and leakage current reduced.